Certain digital signal processors (DSP's) include a random-access memory (RAM) for M-bit data words, a multiplier for multiplying a first, M-bit data word applied at a first input thereof by a second, N-bit data word applied at a second input thereof, with M being greater than N, the output of the RAM being connected to the first input and, through a first temporary storage device, to the second input of the multiplier, and the first temporary storage device being designed to output an applied M-bit data word as two successive partial words of bit lengths N and M-N, respectively. The digital signal processor further comprises an adder following the multiplier and a clock device for controlling data-word transfers.
The above digital signal processor has a simple structure. In particular, it requires few data memories. Thus, it takes up little space, which is particularly advantageous if the digital signal processor is integrated on a semiconductor wafer. In that case, expensive semiconductor material can be saved. Nevertheless, high throughput is ensured. Since the output of the RAM is connected to the first input and, through a temporary storage device, to the second input of the multiplier, two variables provided by the RAM can be multiplied. By the provision of the multiplier, whose second input can only receive an N-bit data word which is shorter than the data word provided by the RAM, further space can be saved.
A digital signal processor of the above type suffers from the drawback that many computing cycles are necessary if many M-bit data words are to be multiplied. For each multiplication, three periods of the clock signal supplied by the clock generator are needed. In the method for performing a multiplication, in a first step, an nth data word is loaded from the RAM into the first temporary storage device. In a second clock period, an n+1st data word transferred from the RAM to the first input of the multiplier is multiplied by the first partial word of the nth data word which is transferred from the first temporary storage device to the second input of the multiplier. In a third clock period, the n+1st data word applied from the RAM to the first input of the multiplier is multiplied by the second partial word of the nth data word which is applied from the first temporary storage device to the second input of the multiplier. These three steps are repeated with the subsequent data words which are taken from the RAM. n is an integer .gtoreq.1. The bus of the RAM is occupied during each clock period.
The object of the invention is to provide a faster digital signal processor of the above type, and a faster method for performing a multiplication using a digital signal processor of the above type.